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PIC18F1230/1330

DS39758D-page 166

2009 Microchip Technology Inc.

15.3.2

EUSART SYNCHRONOUS

MASTER RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either the Single Receive Enable bit,

SREN (RCSTA<5>), or the Continuous Receive

Enable bit, CREN (RCSTA<4>). Data is sampled on the

RX pin on the falling edge of the clock.

If enable bit, SREN, is set, only a single word is

received. If enable bit, CREN, is set, the reception is

continuous until CREN is cleared. If both bits are set,

then CREN takes precedence.

To set up a Synchronous Master Reception:

If any error occurred, clear the error by clearing

bit, CREN.

If using interrupts, ensure that the GIE and PEIE bits

in the INTCON register (INTCON<7:6>) are set.

Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRG16

bit, as required, to achieve the desired baud

rate.

Enable the synchronous master serial port by

setting bits, SYNC, SPEN and CSRC.

Ensure bits, CREN and SREN, are clear.

If the signal from the CK pin is to be inverted, set

the TXCKP bit.

If interrupts are desired, set enable bit, RCIE.

If 9-bit reception is desired, set bit, RX9.

If a single reception is required, set bit, SREN.

For continuous reception, set bit, CREN.

10. Interrupt flag bit, RCIF, will be set when reception

is complete and an interrupt will be generated if

the enable bit, RCIE, was set.

11. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

12. Read the 8-bit received data by reading the

RCREG register.

FIGURE 15-13:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

TABLE 15-8:

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on Page:

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

—

ADIF

RCIF

TXIF

CMP2IF

CMP1IF

CMP0IF

TMR1IF

PIE1

—

ADIE

RCIE

TXIE

CMP2IE

CMP1IE

CMP0IE

TMR1IE

IPR1

—

ADIP

RCIP

TXIP

CMP2IP

CMP1IP

CMP0IP

TMR1IP

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

RCREG

EUSART Receive Register

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

BAUDCON ABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

SPBRGH

EUSART Baud Rate Generator Register High Byte

SPBRG

EUSART Baud Rate Generator Register Low Byte

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

CREN bit

RA3/RX/DT

RA2/TX/CK pin

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

‘0’

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

‘0’

Q1 Q2 Q3 Q4

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

(TXCKP)

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